1. Field of the Invention
The present invention is related to a shift register of an LCD device, and more particularly, to a shift register of an LCD device which reduces leakage.
2. Description of the Prior Art
Liquid crystal display (LCD) devices, characterized in low radiation, thin appearance and low power consumption, have gradually replaced traditional cathode ray tube (CRT) displays and been widely used in electronic products, such as personal digital assistants (PDAs), flat-panel televisions or mobile phones. Traditional LCD devices display images by driving the pixels of the panel using external chips. Recently, the GOA technique, in which the driving circuits are directly fabricated on the LCD panel, has been developed in order to reduce the number of devices and to lower manufacturing costs.
Reference is made to FIG. 1 for a simplified block diagram of a prior art LCD device 100. FIG. 1 only illustrates partial structure of the LCD 100, including a plurality of gate lines GL(1)-GL(N), a shift register 110, a clock generator 120, and a power supply 130. For operating the shift register 110, the clock generator 120 provides a start pulse signal VST and two clock signals CK and XCK, while the power supply 130 provides a bias voltage VSS or VSS′. The clock signals CK and XCK periodically switch between a high voltage level and a low voltage level, and have opposite phases at the same time. The high and low voltage levels of the clock signals CK and XCK are represented by VGH and VGL, wherein VGL is lower than the level of the bias voltage VSS.
The shift register 110 includes a plurality of shift register units SR(1)-SR(N) each having output ends coupled to the corresponding gate lines GL(1)-GL(N), respectively. According to the clock signals CK, XCK and the start pulse signal VST, the shift register 110 can sequentially output gate driving signals GS(1)-GS(N) to the corresponding gate lines GL(1)-GL(N) using the shift register units SR(1)-SR(N), respectively. In the prior art LCD device 100, each shift register unit includes a first pull-down circuit, a second pull-down circuit, an input circuit, a pull-up circuit, and a maintain circuit. The first pull-down circuit includes a first pull-down unit and a first control circuit, while the second pull-down circuit includes a second pull-down unit and a second control circuit.
Reference is made to FIG. 2 for a diagram illustrating an nth-stage shift register unit SR(n) among the plurality of shift register units SR(1)-SR(N), wherein n is an integer between 1 and N. The shift register unit SR(n) includes an input end IN(n), an output end OUT(n), a first pull-down circuit 10, a second pull-down circuit 20, an input circuit 30, a pull-up circuit 40, and a maintain circuit 50. The input end IN(n) of the shift register unit SR(n) is coupled to a prior-stage shift register unit SR(n−1), while the output end OUT(n) of the shift register unit SR(n) is coupled to a next-stage shift register unit SR(n+1) and the gate line GL(n).
The input circuit 30 includes a transistor switch T9, the pull-up circuit 40 includes a transistor switch T10, and the maintain circuit 50 includes a transistor switch T11. The transistor switches T9-T11 can receive the gate driving signal GS(n−1) transmitted from the (n−1)th-stage shift register unit SR(n−1), thereby generating the nth-stage gate driving signal GS(n) accordingly.
In the first pull-down circuit 10, the first control circuit 110 includes transistor switches T1-T3, while the first pull-down unit 120 includes a transistor switch T4. The transistor switches T1-T3 can maintain the gate voltage of the transistor switch T4 according to the clock signals CK, XCK and the gate driving signal GS(n), while the transistor switch T4 can maintain the voltage level of the node Q(n) according to its gate voltage. Since the transistor switches T1 and T2 coupled in series receive the clock signals CK and XCK having opposite phases at respective gate terminals, and the transistor switch T3 receives the gate driving signal GS(n) at its gate terminal, the gate terminal of the transistor switch T4 can be kept at the high voltage level VGH or the low voltage level VSS according to the voltage levels of the clock signals CK, XCK and the gate driving signal GS(n). With the drain terminal coupled to the node Q(n) and the source terminal coupled to the power supply 130 for receiving the low level bias voltage VSS, the transistor switch T4 can control the signal transmission path between the node Q(n) and the low level bias voltage VSS according to its gate voltage.
In the second pull-down circuit 20, the second control circuit 210 includes transistor switches T5-T7, while the second pull-down unit 220 includes a transistor switch T8. The transistor switches T5-T7 can maintain the gate voltage of the transistor switch T8 according to the clock signals CK, XCK and the gate driving signal GS(n), while the transistor switch T8 can maintain the voltage level of the node Q(n) according to its gate voltage. Since the transistor switches T5 and T6 coupled in series receive the clock signals CK and XCK having opposite phases at respective gate terminals, and the transistor switch T7 receives the gate driving signal GS(n) at its gate terminal, the gate terminal of the transistor switch T8 can be kept at the high voltage level VGH or the low voltage level VGL according to the voltage levels of the clock signals CK, XCK and the gate driving signal GS(n). With the drain terminal coupled to the node Q(n) and the source terminal coupled to the power supply 430 for receiving the low level bias voltage VSS, the transistor switch T8 can control the signal transmission path between the node Q(n) and the low level bias voltage VSS according to its gate voltage.
Except during the nth-stage output period, the node Q(n) needs to be kept at low level for turning off the transistor switch T10. With the first pull-down circuit 11 and the second pull-down circuit 21 each in charge of 50% of the pull-down operation, the gate driving signal GS(n) can thus be maintained at low level. The pull-down operation is performed by the first pull-down circuit 11 when the clock signal CK is at high level. The transistor switch T1 is turned on and the transistor switch T2 is turned off, thereby pulling up the gate terminal of the transistor switch T4 to the high voltage level VGH of the clock signal CK via the turned-on transistor switch T1. Therefore, the transistor switch T4 can be turned on for pulling down the node Q(n) to the low voltage level VSS. On the other hand, the pull-down operation is performed by the second pull-down circuit 21 when the clock signal XCK is at high level. The transistor switch T5 is turned on and the transistor switch T6 is turned off, thereby pulling up the gate terminal of the transistor switch T8 to the high voltage level VGH of the clock signal XCK via the turned-on transistor switch T5. Therefore, the transistor switch T8 can be turned on for pulling down the node Q(n) to the low voltage level VSS. On the other hand, when the first pull-down circuit 11 is not performing the pull-down operation, the gate terminal of the transistor switch T4 is kept at the low voltage level VGL of the clock signal XCK during the time other than the nth-stage output period, while the gate terminal of the transistor switch T8 is kept at the low voltage level VGL of the clock signal CK during the time other than the nth-stage output period.
During the nth-stage output period, the node Q(n) needs to be kept at high level so that the transistor switch T10 can be turned on for outputting high level gate driving signal GS(n). In order to stop the first pull-down circuit 11 and the second pull-down circuit 21 from performing the pull-down operation, the transistor switches T4 and T8 need to be turned off. In other words, the gate terminals of the transistor switches T4 and T8 are kept at the low voltage level VSS using the transistor switches T3 and T7 when the gate driving signal GS(n) is at high level. However, it takes time for the gate terminals of the transistor switches T4 and T8 to be pulled down to VSS from VGH. During this transient period, the transistor switch T2 may not be completely turned on due to possible leakage at the node Q(n). As a result, the gate driving signal GS(n) may not be able to reach ideal voltage level.
Reference is made to FIG. 3 for a diagram illustrating another prior art nth-stage shift register unit SR(n) among the plurality of shift register units SR(1)-SR(N), wherein n is an integer between 1 and N. The shift register unit SR(n) includes an input end IN(n), an output end OUT(n), a first pull-down circuit 16, a second pull-down circuit 26, an input circuit 30, a pull-up circuit 40, and a maintain circuit 50. In the shift register unit SR(n) depicted in FIGS. 2 and 3, the input circuit 30, the pull-up circuit 40 and the maintain circuit 50 have similar structure and operation. The first pull-down circuit 16 also includes a first control circuit 110 and a first pull-down unit 120, wherein the transistor switches T1-T4 have similar structure as depicted in FIG. 2. However, a low level bias voltage VSS is applied to the source terminals of the transistor switches T3 and T4, while a low level bias voltage VSS′ is applied to the source terminal of the transistor switch T2. On the other hand, the second pull-down circuit 26 also includes a second control circuit 210 and a second pull-down unit 220, wherein the transistor switches T5-T8 have similar structure as depicted in FIG. 2. However, the low level bias voltage VSS is applied to the source terminals of the transistor switches T7 and T8, while the low level bias voltage VSS′ is applied to the source terminal of the transistor switch T6. The bias voltage VSS and VSS′ have different voltage levels.
Except during the nth-stage output period, the low level bias voltage VSS′ can accelerate the pull-down operation performed by the transistor switches T2 and T6. However, during the nth-stage output period, it still takes time for the gate terminals of the transistor switches T4 and T8 to be pulled down to VSS from VGH. During this transient period, the transistor switch T2 may not be completely turned on due to possible leakage at the node Q(n). As a result, the gate driving signal GS(n) may not be able to reach ideal voltage level.